1. Field of the Invention
The present invention relates to processors, and more particularly to processors executing floating point instructions
2. Description of the Related Art
It is known to provide a computer architecture with a single instruction stream multiple data stream (SIMD) architecture. A SIMD architecture is a computer architecture that performs one operation on multiple sets of data, for example, an array processor. One computer or processor is used for the control logic and the remaining processors are used as slaves, each executing the same instruction.
It is known to provide a VIS Instruction Set for executing on processors. The VIS instruction set is a set of RISC instructions which are extensions to the SPARC V9 open processor architecture and are designed to accelerate applications where multiple data entries require the same instruction, such as; multimedia, image processing and networking applications. The VIS Instruction Set is SIMD code embedded in, for example, UltraSPARC processors.
The VIS 3.0 instruction set architecture defines several single precision floating point instructions which execute as a SIMD operation. These instructions produce two independent 32-bit single precision results in parallel. Each 64-bit source register for the SIMD instructions contains two 32-bit single precision floating point values.
It is known for a processor implementing the VIS 3.0 instruction set to execute a two way SIMD single precision floating point add instruction (e.g., a SFADD instruction). With such an instruction, it is desirable to provide aligner and normalizer shifters within the floating point unit to operate on two independent sets of single precision data. It is also desirable for these shifters to support a conventional double precision operation having one wider floating point value